Regviz

Freescale Semiconductor /MKW40Z4 /XCVR /RX_DIG_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RX_DIG_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKW40Z4/XCVR/RX_DIG_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RX_ADC_NEGEDGE 0 (0)RX_CH_FILT_BYPASS 0 (0)RX_ADC_RAW_EN 0 (0)RX_DEC_FILT_OSR 0 (0)RX_INTERP_EN 0 (0)RX_NORM_EN 0 (0)RX_RSSI_EN 0 (0)RX_AGC_EN 0 (0)RX_DCOC_EN 0 (0)RX_DCOC_CAL_EN 0 (0)RX_IQ_SWAP

RX_IQ_SWAP=0, RX_AGC_EN=0, RX_ADC_RAW_EN=0, RX_CH_FILT_BYPASS=0, RX_DEC_FILT_OSR=0, RX_ADC_NEGEDGE=0, RX_DCOC_EN=0, RX_NORM_EN=0, RX_DCOC_CAL_EN=0, RX_INTERP_EN=0, RX_RSSI_EN=0

Description

RX Digital Control

Fields

RX_ADC_NEGEDGE

Receive ADC Negative Edge Selection

0 (0): Register ADC data on positive edge of clock

1 (1): Register ADC data on negative edge of clock
RX_CH_FILT_BYPASS

Receive Channel Filter Bypass

0 (0): Channel filter is enabled.

1 (1): Disable and bypass channel filter.
RX_ADC_RAW_EN

ADC Raw Mode selection

0 (0): Normal operation.

1 (1): The decimation filter’s 12bit output consists of two unfiltered 5-bit ADC samples. This is for test purposes only to observe ADC output via XCVR DMA or DTEST.
RX_DEC_FILT_OSR

Decimation Filter Oversampling

0 (0): OSR 2

1 (1): OSR 4

2 (10): OSR 8

3 (11): OSR 9

4 (100): OSR 16

5 (101): OSR 18
RX_INTERP_EN

Interpolator Enable

0 (0): Interpolator is disabled.

1 (1): Interpolator is enabled.
RX_NORM_EN

Normalizer Enable

0 (0): Normalizer is disabled.

1 (1): Normalizer is enabled.
RX_RSSI_EN

RSSI Measurement Enable

0 (0): RSSI measurement is disabled.

1 (1): RSSI measurement is enabled.
RX_AGC_EN

AGC Global Enable

0 (0): AGC is disabled.

1 (1): AGC is enabled.
RX_DCOC_EN

DCOC Enable

0 (0): DCOC is disabled.

1 (1): DCOC is enabled.
RX_DCOC_CAL_EN

DCOC Calibration Enable

0 (0): DCOC calibration is disabled.

1 (1): DCOC calibration is enabled.
RX_IQ_SWAP

RX IQ Swap

0 (0): IQ swap is disabled.

1 (1): IQ swap is enabled.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data